Several serial bus technologies and methodologies have been developed and incorporated into protocol standards to allow functional control, operation, configuration and test of semiconductor devices. Some of the more popular protocol standards include the Inter-IC (I2C) bus specification developed by Phillips Semiconductors, the serial peripheral interface (SPI) standard developed by Motorola Inc., the Joint Test Access Group (JTAG) standard embodied as the 1149.1 IEEE standard, and recommended standard-232C (RS-232) approved by the Electronic Industries Association (EIA) for connecting serial devices. Nevertheless, implementation of semiconductor devices with protocol specific serial interfaces have proved burdensome in electronic applications that utilize a backplane assembly to transmit clock signals, data signals, and control lines to multiple circuit card assemblies connected to the backplane assembly. Moreover, because there are multiple serial interface standards, the electronic apparatus must incorporate multiple serial busses in the backplane assembly to support the various serial data transfer protocols.
Moreover, each serial interface standard identified includes its own unique limitations that further hinder implementation of mixed serial interface standards in an electronic apparatus having a backplane assembly. For example, JTAG enhanced semiconductor devices require an uninterruptable serial chain to couple each device in order to pass data from one device to another. Hence, when a JTAG serial bus is incorporated into a backplane assembly, removal of a circuit card assembly having JTAG enhanced semiconductor devices from the backplane assembly breaks the JTAG serial chain and leaves the remainder of the JTAG serial chain non-functional. Although JTAG enhancements targeting the backplane environment can be implemented, such as an addressable shadow port (ASP) or bus extenders with switchable bus isolation switches, the enhancements are burdensome to control and monitor.
With regard to I2C semiconductor devices, the I2C standard utilizes a limited addressability bus that allows no more than eight I2C semiconductor devices per bus. Thus, a backplane assembly must include multiple I2C buses to compensate for the limited addressability of the I2C standard.
With regard to the SPI semiconductor devices, the SPI standard requires an individual chip select for each SPI semiconductor device. As a result of the individual chip select requirement, SPI semiconductor devices are often unsuitable for direct connection with a remote master controller.